In semiconductor and packing technologies, silicon is used in either single crystal or polycrystalline form. Further, metal silicids are used for many purposes, such as gate electrodes, ohmic contacts, interconnection lines, and Schottky barrier diode contacts. As examples of these various uses, reference is made to the following patents and publications which form a background for the present invention:
U.S. Pat. Nos. 4,180,596, 4,329,706 4,389,257; 3,927,225.
K. L. Wang et al, "Composite TiSi.sub.2 /n.sup.+ poly-Si Low Resistivity Gate Electrode and Interconnect for VLSI Device Technology", International Electron Devices Meeting (IEDN), Washingtion, D.C., Dec. 7-9, 1981 (Proceedings Thereof, pages 58-61).
B. L. Crowder et al, IBM Technical Disclosure Bulletin, 20, No. 6, page 2455, November 1977.
D. R. Campbell et al, IBM Technical Disclosure Bulletin, 25, No. 12, page 6624, May 1983.
As is apparent from these references, many different metals have been used to make the metal silicides. These metals include W, Ta, Mo, Ti, Nb, Rh, Pt, Pd, Co, rare earth metals, etc. Also, different phases of the metal silicides have been used in the past as noted by the following two publications:
M. Wittmer, J. Appl. Phys, 54, (9), page 5081, September 1983.
M. Wittmer and K. N. Tu, Physical Review B, 27, No. 2, page 1173, Jan. 15, 1983.
These two publications describe the growth kinetics for platinum silicide and palladium silicide and describe the influence of substrate orientation and silicide dopant. These and other references point out that the resistivity of the silicide, for any metal, often depends on the particular silicide phase which is formed. For example, PtSi may have a different resistivity than Pt.sub.2 Si.
In the prior art, metal silicides have been formed by a variety of techniques including codeposition (such as cosputtering and coevaporation), chemical vapor deposition (CVD), and thermal annealing of a metal layer deposited on a silicon substrate. When metal silicides are deposited by coevaporation or cosputtering they are in an amorphous form, and are then annealed at high temperatures (typically 700.degree. C.-1200.degree. C.) in order to make the silicide crystalline and to lower its resistivity.
References which describe codeposition of metal silicides include the aforementioned U.S. Pat. Nos. 4,389,257 and 4,329,706, as well as the K. L. Wang et al publication. Aforementioned U.S. Pat. No. 3,927,225 described thermal processes for producing metal silicides, where the metal (Pt) is either deposited on a silicon substrate and then heated, or deposited on a heated substrate. The growth of metal silicides formed by these thermal processes is described in detail in terms of its growth kinetics and diffusion by the aforementioned Wittmer and Wittmer et al publications.
In the prior art, it is possible to determine which metal silicide phase will be formed, and to control the silicide formation process such that a particular silicide phase will be formed. For example, in the thermal process wherein a metal layer is deposited on silicon and then annealed to grow a metal silicide, using particular temperature ranges will produce specified metal silicide phases. An illustration of this is the growth of TiSi.sub.2 on silicon by depositing a layer of Ti thereon and annealing in the temperature range of approximately 500.degree.-700.degree. C. Another example is the formation of PtSi by annealing a Pt layer on silicon at a temperature range 400.degree.-550.degree. C. If a lower temperature range (200.degree.-350.degree. C.) is used, the phase Pt.sub.2 Si will be formed.
For deposition techniques involving coevaporation or cosputtering, the relative amounts of metal and silicon in the sources (or targets) are adjusted to provide the desired stiochiometric proportions of silicon and metal in the metal silicide compound. It is not possible to use the same process to form different metal silicide phases simultaneously in different parts of a device, chip, or wafer. If different silicide phases are desired, different annealing steps must be undertaken, or additional co-deposition steps are required. Another alternative in the prior art is to use different metals to form different silicides in different locations. Of course, this also requires more complicated processing.
In this technology, it is often the situation that different resistivities are required for metal silicides in different portions of the chip or wafer. For example, a metal silicide Schottky barrier contact will require a different resistivity than a metal silicide used either as an interconnect line or as an ohmic contact.
In the prior art, there is no way to easily tailor the resistivity of the metal silicide in accordance with its use, if the same metal is used to form multiple metal silicide layers. Thus, if it is desired to fabricate VLSI structures or to fabricate different devices on the same chip, different metallurgical combinations and/or processing steps have heretofore been required.
Accordingly, it is a primary object of this invention to provide a silicon substrate-metal silicide combination in which the phase of the metal silicide is dependent upon the dopant and doping level of the substrate.
It is another object of this invention to provide a process for forming different phases of metal silicide in different portions of a semiconductor device, chip, or wafer, using the same metal throughout and the same processing steps.
It is another object of this invention to provide a new, additional control for metal silicide formation in order to determine the phase of the metal silicide compound which is formed.
It is another object of the present invention to provide different compound phases of a metal silicide, where the phase which is formed is dependent upon a property of the silicon substrate.
It is a further object of this invention to provide an improved annealing (thermal) technique for forming metal silicides, where an additional degree of control is provided in order to determine the phase of the metal silicide compound which is formed.
It is a still further object of this invention to provide an improved annealing technique for forming metal silicides on a silicon substrate, wherein the resistivity of the metal silicides so formed can be controlled.
It is another object of this invention to provide a technique for the growth of metal silicides on a substrate, which can be used to provide different compound phases of a metal silicide, in accordance with the application for which the metal silicide is used.
It is a further object of this invention to provide an improved technique for the growth of a metal silicide by thermal processes, wherein the phase of the metal silicide compound which is formed is controlled by a property of the silicon substrate.
It is another object of the present invention to use a single constituent metal layer for the growth of metal silicide on a silicon substrate, wherein different metal silicide phases can be formed on different regions of the substrate in a single process.
It is another object of the present invention to provide metal silicide-silicon substrate combinations wherein the phase of the metal silicide formed on the silicon substrate by thermal processing of a metal on the substrate is determined by the dopant and by the level of doping concentration at the metal-silicon interface during silicide formation.